1. Field of the Invention
The present invention relates to an information processing unit provided with an asynchronous protocol conversion function.
2. Description of the Related Art
An information processing unit provided with a conventional type asynchronous protocol conversion function realized data sending/receiving by handshaking for a request to send data and data acceptance authentication when the data was sent/received. Therefore, many processing cycles occurred in handshaking and as a result, data transmission efficiency was deteriorated. Conventional type information processing will be described below. FIG. 22 is a block diagram showing the configuration of the conventional type information processing unit and a data transmission situation and FIGS. 23, 24 and 25 show their waveforms.
As shown in FIG. 22, the conventional type information processing unit includes registers (flip-flops) 1a to 1e controlled by a clock on the side of a master (a transmission source), registers 2a to 2e controlled by a clock on the side of a slave (a transmission destination), logics 3 to 6 for protocol conversion and circuit control, a bus 7 for transmitting a data transmission signal, a bus 8 for transmitting a data transmission completion signal and a bus 9 for transmitting a data signal.
The data transmission signal is a control signal sent from the master's side to the slave's side prior to transmitting a data signal from the master's side to the slave's side according to a handshaking protocol for requesting circuit assurance. The data transmission completion signal is a post signal sent from the slave's side to the master's side to authorize the transmission of the next data signal in case the transmission of the data signal is completed.
In an asynchronous protocol conversion bridge shown in FIG. 22, a clock system on the master's side and a clock system on the slave's side are different and a clock boundary exists between the master's side and the slave's side. In such a case, on a clock boundary of the bus 7 on which the data transmission signal is transmitted, one register 1b and two cascaded registers 2a are arranged in pairs in a direction of transmission, on a clock boundary of the bus 8 on which the data transmission completion signal is transmitted, one register 2c and two cascaded registers 1d are arranged in pairs in the direction of transmission, and further, on a clock boundary of the bus 9 on which the data signal is transmitted, one register 1e and two cascaded registers 2e are arranged in pairs in the direction of transmission.
The reason why each register 1b, 2c, 1e is arranged before each clock boundary is to absorb the delay of each signal caused by the protocol conversion and the reason why each two cascaded registers 2a, 1d, 2e are arranged after each clock boundary is to absorb an unstable edge caused by the clock conversion.
The operation of the information processing unit configured as described above will be described below. The registers 1a to 1e on the master's side are operated according to a clock on the master's side and respective signals are delayed by one clock cycle on the master's side when they pass the registers 1a to 1e on the master's side. Similarly, the registers 2a to 2e on the slave's side are operated according to a clock on the slave's side and respective signals are delayed by one clock cycle on the slave's side when they pass the registers 2a to 2e on the slave's side.
Therefore, as shown by the waveforms in FIGS. 23, 24 and 25, in case the data transmission signal and the data signal are sent from a transmission source bus, it takes two master cycles until the data transmission signal reaches the clock boundary and it takes three slave cycles until the data transmission signal reaches the transmission destination bus from the clock boundary.
After so as to transmit the completion of data transmission to the transmission source bus, it takes two slave cycles until the data transmission completion signal reaches the clock boundary from the transmission destination bus and it takes three master cycles until the data transmission completion signal reaches the transmission source bus from the clock boundary, control is passed to the next data transmission. Incidentally, it takes one master cycle until the data signal reaches the clock boundary from the transmission source bus and it takes two slave cycles until the data signal reaches the transmission destination bus from the clock boundary.
Therefore, the number of cycles required until one data is transmitted and a command for the next data is issued is “5 master cycles+5 slave cycles”. Asynchronous data transmission/reception is performed by repeating the above-mentioned processing.
In the meantime, there is also an example in which data transmission between different CPU system buses and between different PCI bus architectures is optimized and the efficiency is enhanced (refer to JP-A-348647 (FIG. 1)).
However, in the above-mentioned conventional type asynchronous protocol conversion circuit, to correspond to a case that the master is quick and the slave is slow, a case that the master is slow and the slave is quick and a case that the master is quick and the slave is quick, a protocol conversion logic is required to be arranged both on the master's side and on the slave's side, therefore multiple registers are required, the number of clock cycles required for sending/receiving the data transmission signal is increased, and as a result, data transmission efficiency is deteriorated.
Besides in related art, correspondence to a case that no data signal is transmitted soon after negotiation (circuit assurance) by the data transmission signal from the master's side is required, therefore the number of protocol conversion logics is increased, their speedup becomes difficult, and as a result, the data transmission efficiency is deteriorated.
In the meantime, the technique described in the patent document 1 is limited to data transmission between different CPU system buses on a motherboard and others and between different PCI bus architectures and it is difficult to apply the technique to an on-chip bus in an integrated circuit as it is.